Digital signal processors (DSPs) are special-purpose microcomputers which are uniquely designed to perform digital signal processing at high rates. These high processing rates enable DSPs to implement digital filters and compute fast fourier transforms. In the past, various types of instruction sets have been used for achieving high processing rates for DSPs.
One popular type of instruction set includes instructions which have a type code field and an operation code field to define the specific operations to be performed by the DSP. The type code field for an instruction identifies its instruction type. The operation code field identifies from among the operations that can be executed with the instruction type the specific operations that are to be executed by the instruction. The bit length of each instruction is fixed. In addition, the bit length of the type code field is either fixed or varies only slightly for different instruction types. The same is true of the operation code field.
Another popular type of instruction set uses instructions that have only an operation code field to identify the specific operations the DSP is called on to perform. As is the case with the other instruction set described earlier, the bit length of each instruction is fixed and the operation code field is either fixed or varies only slightly for different instructions.
In order to achieve high processing rates, the remaining fields in the instructions of the described instruction sets may include operand source and destination fields for data processing operations and/or address source fields and operand source or destination fields for memory access data transfer operations. Some of the instructions of these instruction sets include both operand source and destination fields for data processing operations and address source fields and operand source or destination fields for data transfer operations. Thus, these types of instructions define data processing operations in parallel with data transfer operations. However, other instructions in these instruction sets include only operand source and destination fields for data processing and still other instructions include only address source and operand source or destination fields for memory related data transfer operations.
The fixed or limited variable bit lengths of the type codes and/or operation codes of the instructions of these instruction sets take up many of the fixed number of bits of the instructions. As a result, the number of bits left for the remaining fields of the instructions is limited. This limits programming flexibility in a number of critical ways.
For example, it may be desired to have large flexibility in selecting operand sources and destinations for data processing operations and/or large flexibility in selecting address sources and operand sources or destinations for memory access data transfer operations. In order to achieve this kind of flexibility, the bit length of the operand source and destination fields and the address source fields must be large. As a result, the number of parallel operations defined by a fixed bit length instruction is sacrificed in order to accommodate the large bit lengths of these fields.
Alternatively, it may be desired to have many parallel operations defined by a fixed bit length instruction. In this case, the bit lengths of operand source and destination fields and address source fields may be very limited. Thus, flexibility in selecting operand sources and destinations for data processing operations and flexibility in selecting address sources and operand sources or destinations for data transfer operations may be sacrificed.
Furthermore, the distinction between various operand source and destination fields for data processing operations may be eliminated for instructions that define many parallel operations. Thus, the flexibility in selecting separate operand sources and destinations for data processing operations will be eliminated as well.
This sacrificing of programming flexibility could be avoided by increasing the bit length of the instructions of an instruction set. However, the use of longer instructions necessarily will result in increased program storage (i.e., memory) costs. Furthermore, pre-processors and other hardware could be utilized to create longer instruction words only in particular situations. While helpful in adding some flexibility, the resultant increase in overhead and more costly program storage (although minimized) is not desirable.
In the competitive digital signal processor market, the ability of a processor to pipeline instructions is one measure of processor performance. Pipelining is the process of decomposing repetitive processes within the processor into subprocesses that can be executed concurrently and in an overlapping fashion. Two distinct limitations exist in the ability to pipeline instructions. The first is software (i.e., programming) limitations and the second is hardware limitations.
Hardware limitations to pipelining arise when the DSP's hardware physically restricts the operation of the DSP. This type of pipelining limitation may be manifest or hidden. Hardware limitations that are manifest occur when the data paths of the DSP restrict access to existing operand sources, operand destinations, or address sources. Hardware limitations that are hidden occur when an instruction which is written as if it can be performed in a single clock (i.e., machine) cycle can in fact only be performed in two or more cycles because of hardware limitations.
Software limitations on the other hand prevent the programmer from pipelining instructions and making use of existing processor hardware or capabilities. This occurs when the instruction set (i.e., instruction format) does not give the programmer the flexibility to (1) select from all of the available operand sources and destinations for data processing operations or from all of the available address sources and operand sources or destinations for data transfer operations, (2) select separate operand sources and destinations for data processing operations, or (3) implement many parallel operations with one instruction. In the case of (1) and (2), extra instructions must be used to move operands or addresses to or from desired sources or destinations. In the case of (3), extra instructions must be executed to perform those operations which could not be performed in parallel with the operations of other instructions.